Semiconductor Devices Including Transistors Having Recessed Channels

ABSTRACT

Semiconductor devices including an isolation layer on a semiconductor substrate are provided. The isolation layer defines an active region of the semiconductor substrate. The device further includes an upper gate electrode crossing over the active region and extending to the isolation layer and lower active gate electrode. The lower active gate electrode includes a first active gate electrode extending from the upper gate electrode to the active region and a second active gate electrode below the first active gate electrode and having a greater width than a width of the first active gate electrode. The device further includes a lower field gate electrode that extends from the upper gate electrode to the isolation layer and has a bottom surface that is at a lower level than a bottom surface of the active gate electrode such that the sidewalls of the active region are covered below the lower active gate electrode. Related methods of fabricating semiconductor devices are also provided herein.

REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.11/704,872, filed Feb. 9, 2007, which claims priority to Korean PatentApplication No. 2006-0058818, filed Jun. 28, 2006, the disclosures ofwhich are hereby incorporated herein by reference as if set forth intheir entirety.

FIELD OF THE INVENTION

The present invention generally relates to semiconductor devices and,more particularly, to semiconductor devices including transistors andrelated methods.

BACKGROUND OF THE INVENTION

Semiconductor devices may use discrete devices, such as field effecttransistors (FETS), as switching devices. In the transistor, anon-current formed in a channel between source and drain regions of thedevice typically determines the operating speed of the device. Normally,a planar-type transistor may be provided by forming a gate electrode andsource/drain regions on a substrate on which a device will be formed,for example, an active region. A typical planar-type transistor has aplanar channel between the source/drain regions. The on-current of theplanar-type transistor is typically proportional to a width of theactive region, and is typically inversely proportional to a distancebetween the source and drain regions, i.e., a gate length. Thus, inorder to increase the operating speed of a device by increasing theon-current, a length of a gate is typically decreased, and a width of anactive region is typically increased. However, increasing the width ofthe active region in the planar-type transistor may increase the overallsize of the device, which may be incompatible with the trend in thesemiconductor fabrication industries to develop semiconductor devices ofincreasingly higher integration density.

Furthermore, the planar-type transistor may experience a short channeleffect when a distance between source and drain regions in theplanar-type transistor is shortened. Therefore, generation of the shortchannel effect typically must be effectively suppressed in order toprovide a transistor having a short channel length suitable for a nextgeneration semiconductor device. However, since a conventionalplanar-type transistor, where a channel is formed in parallel with thesurface of a semiconductor substrate, is a flat-type channel device, thestructure may be unfavorable to the scale-down of the device, and it maybe difficult to suppress generation of the short channel effect as well.

To address the problems of the short channel effect, and scale down thetransistor, a transistor having a recessed channel has been proposed.The recessed channel transistor may include a recessed channel regionand an insulated gate electrode. The recessed channel transistor mayprovide a relatively effective channel length compared to that of aplanar-type transistor. In other words, the recessed channel transistormay provide a structure capable of solving the problems due to the shortchannel effect. However, the recessed channel transistor may haveunfavorable defects compared to the planar-type transistor, such as anincreased threshold voltage and/or operating speed.

SUMMARY OF THE INVENTION

Some embodiments of the present invention provide semiconductor devicesincluding an isolation layer on a semiconductor substrate. The isolationlayer defines an active region of the semiconductor substrate. Thedevice further includes an upper gate electrode crossing over the activeregion and extending to the isolation layer and lower active gateelectrode. The lower active gate electrode includes a first active gateelectrode extending from the upper gate electrode to the active regionand a second active gate electrode below the first active gate electrodeand having a greater width than a width of the first active gateelectrode. The device further includes a lower field gate electrode thatextends from the upper gate electrode to the isolation layer and has abottom surface that is at a lower level than a bottom surface of theactive gate electrode such that the sidewalls of the active region arecovered below the lower active gate electrode.

In further embodiments of the present invention, the lower field gateelectrode may include a first field gate electrode and a second fieldgate electrode below the first field gate electrode. The second fieldgate electrode may have a greater width than a width of the first fieldgate electrode. An upper surface of the second field gate electrode maybe higher than a bottom surface of the second active gate electrode.

In still further embodiments of the present invention the second fieldgate electrode may have a larger width than a width of the first activegate electrode. The second field gate electrode may have a larger widththan a width of the second active gate electrode.

In some embodiments of the present invention, the lower field gateelectrode may cover at least one sidewall of an active region located onboth sides of the lower active gate electrode.

In further embodiments of the present invention, a first impurity regionand a second impurity region may be provided in an active region locatedon both sides of the first upper gate electrode. The first impurityregion and the second impurity region may have an asymmetric structure.The first impurity region may have a shallow junction structure relativeto a junction structure of the second impurity region. The firstimpurity region may have an impurity density lower than an impuritydensity of the second impurity region.

In still further embodiments of the present invention, a high densitychannel impurity region may be provided below the second impurityregion. The high density channel impurity region may have a differentconductivity type from a conductivity type of the first and secondimpurity regions. The high density channel impurity region may have animpurity density higher than an impurity density of a channel regionbelow the first impurity region.

In some embodiments of the present invention a data storage elementelectrically connected to the first impurity region may be provided inthe semiconductor device.

Although embodiments of the present invention are primarily discussedabove with respect to semiconductor devices, methods of fabricatingsemiconductor devices are also provided herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of semiconductor devices according to someembodiments of the present invention.

FIGS. 2A through 6C, and FIG. 7 are cross-sections illustratingsemiconductor devices according to some embodiments of the presentinvention.

FIGS. 8A through 11C are cross-sections illustrating semiconductordevices according to some embodiments of the present invention.

FIG. 12 is a cross-section illustrating semiconductor devices accordingto some embodiments of the present invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity. It will beunderstood that when an element or layer is referred to as being “on”,“connected to” or “coupled to” another element or layer, it can bedirectly on, connected or coupled to the other element or layer orintervening elements or layers may be present. In contrast, when anelement is referred to as being “directly on,” “directly connected to”or “directly coupled to” another element or layer, there are nointervening elements or layers present. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Like numbers refer to like elements throughout.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

It will be understood that although the terms first and second are usedherein to describe various elements, these elements should not belimited by these terms. These terms are only used to distinguish oneelement from another element.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention.The thickness of layers and regions in the drawings may be exaggeratedfor clarity. Additionally, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a discrete change from implanted to non-implanted regions.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andthis specification and will not be interpreted in an idealized or overlyformal sense unless expressly so defined herein.

FIG. 1 is a plan view of a semiconductor device according to someembodiments of the present invention, FIGS. 2A through 6C and FIG. 7 arecross-sections of semiconductor devices according to some embodiments ofthe present invention, FIGS. 8A through 11C are cross-sections ofsemiconductor devices according to some embodiments of the presentinvention, and FIG. 12 is a cross-section of semiconductor devicesaccording to some embodiments of the present invention. Furthermore,FIGS. 2A, 3A, 4A, 5A, 6A, 7, 8A, 9A, 10A, 11A and 12 are cross-sectionstaken along line I-I′ of FIG. 1, FIGS. 2B, 3B, 4B, 5B, 6B, 8B, 9B, 10Band 11B are cross-sections taken along line II-II′ of FIG. 1, and FIGS.2C, 3C, 4C, 5C, 6C, 8C, 9C, 10C and 11C are cross sections taken alongline III-III′ of FIG. 1.

Referring first to FIGS. 1 and 6A through 6C, semiconductor devicesaccording to some embodiments of the present invention will bediscussed. As illustrated in FIGS. 1 and 6A through 6C, an isolationlayer 109 is provide on a semiconductor substrate 100. The semiconductorsubstrate has an active region A and a field region F. The isolationlayer 109 may be provided in the semiconductor substrate of the fieldregion F, so as to define a plurality of active regions A. In someembodiments of the present invention, the isolation layer 109 may be ashallow trench isolation layer. The active regions A may be provided tohave a major axis and a minor axis, and the active regions A may bealigned two-dimensionally in the major axis direction and the minor axisdirection.

An insulating liner 106 may be provided between the isolation layer 109and the semiconductor substrate 100. The insulating liner 106 may beinclude an insulating layer, such as a silicon nitride layer. A bufferoxide layer 103 may be provided between the insulating liner 106 and thesemiconductor substrate 100. The buffer oxide layer 103 may include aninsulating layer, such as a silicon oxide layer.

Upper gate electrodes UG, which cross the active region A and extend tothe isolation layer 109, may be provided. In some embodiments of thepresent invention, the upper gate electrode UG provided on the activeregion A is defined as an upper active gate electrode 157 a, and theupper gate electrode UG provided on the isolation layer 109 is definedas an upper field gate electrode 157 b.

A lower active gate electrode 155 a is provided. The lower active gateelectrode 155 a includes a first active gate electrode 154, whichextends from the upper active gate electrode 157 a into the substrate ofthe active region A, and a second active gate electrode 151, which islocated below the first active gate electrode 154 and has a greaterwidth than that of the first active gate electrode 154. For example, thesecond active gate electrode 151 may have a circular shape asillustrated in the cross-section of FIG. 6A. Thus, the electric fieldcrowding phenomenon between the second active gate electrode 151 and theactive region A may be suppressed. Furthermore, since the second activegate electrode 151 has a width greater than that of the first activegate electrode 154, the transistor may have an increased effectivechannel length.

A lower field gate electrode 155 b may be provided that extends from theupper field gate electrode 157 b to the isolation layer 109. The lowerfield gate electrode 155 b has a bottom surface that is at the levellower than that of the second active gate electrode 151 so as to coverthe sidewalls of the active region located below the second active gateelectrode 151. Thus, the active region located below the second activegate electrode 151 may have a fin structure.

The lower active gate electrode 155 a and the lower field gate electrode155 b may form a lower gate electrode LG. A metal layer 160 may bedisposed on the upper active gate electrode 157 a and the upper fieldgate electrode 157 b. The metal layer 160 may include, for example, acobalt (Co) layer, a tungsten (W) layer, a titanium (Ti) layer, a nickel(Ni) layer, or a metal silicide layer. The upper gate electrode UG, thelower gate electrode LG, and the metal layer 160 may form a gateelectrode 161. The upper active gate electrode 157 a, the lower activegate electrode 155 a, the upper field gate electrode 157 b, and thelower field gate electrode 155 b may include, for example, a conductivelayer, such as a polysilicon layer.

A gate electrode located between the active regions A aligned in themajor axis direction may be an upper field gate electrode 157 b. A gatedielectric layer 148 may be provided between the gate electrode 161 andthe semiconductor substrate 100. The gate dielectric layer 148 mayinclude, for example, a silicon oxide layer or a high-k dielectriclayer.

First and second impurity regions 167 s and 167 d may be provided in theactive region located at both sides of the gate electrode 161. The firstimpurity region 167 s and the second impurity region 167 d may have anasymmetric structure. For example, the first impurity region 167 s mayhave a shallow junction compared to the second impurity region 167 d.Furthermore, the first impurity region 167 s may have an impuritydensity lower than that of the second impurity region 167 d.

Furthermore, a high density channel impurity region 168 may be disposedbelow the second impurity region 167 d. The high density channelimpurity region 168 may have a conductivity type different from those ofthe first and second impurity regions 167 s and 167 d, and may have animpurity density higher than that of a channel region below the firstimpurity region 167 s.

As discussed above, since the lower active gate electrode 155 a isdisposed in the active region A, a transistor may be provided having anincreased effective channel length. Furthermore, since the lower fieldgate electrode 155 b on the sidewalk of the active region located belowthe lower active gate electrode 155 a is provided, a transistor may beprovided having an increased channel width. Therefore, a field effecttransistor capable of increasing an effective channel length and aneffective channel width may be provided according to some embodiments ofthe present invention.

Referring now to FIG. 7, a data storage element 187, which iselectrically coupled to the first impurity region 167 s, may beprovided. The data storage element 187 may include, for example, a lowerelectrode, a data storage media, and an upper electrode. In someembodiments of the present invention, the data storage media may be acapacitor dielectric layer or a resistance material layer.

A buried contact plug 184 may be provided between the data storageelement 187 and the first impurity region 167 s. A first landing pad 169s may be provided between the buried contact plug 184 and the firstimpurity region 167 s.

A conductive line 178, which is electrically connected to the secondimpurity region 167 d, may be provided. A direct contact plug 175 may beprovided between the conductive line 178 and the second impurity region167 d. A second landing pad 169 d may be provided between the directcontact plug 175 and the second impurity region 167 d.

When the data storage element 187 includes a capacitor dielectric layer,semiconductor devices according to some embodiments of the presentinvention may be used for a memory device, such as a dynamic randomaccess memory (DRAM). When the semiconductor device of the presentinvention is used for a memory device such as a DRAM, the electricalproperty of the memory device may be improved. In particular, sincesemiconductor devices according to some embodiments of the presentinvention may have an increased effective channel length, a shortchannel effect may be reduce or even suppressed, and since semiconductordevices according to some embodiments of the present invention may havean increased effective channel width, a current driving capability maybe improved. Furthermore, since the transistor may be provided to have afin structure, variation of threshold voltages by a body effect can bereduced even though the transistor has a recessed channel. Furthermore,since the gate electrode 161 may include a metal layer 160, it may behelpful to improve a signal transmission rate. Therefore, transistorshaving improved operating speeds while suppressing the short channeleffect may be provided.

Furthermore, since the first impurity region 167 s and the secondimpurity region 167 d have an asymmetric structure, characteristics ofthe memory device can be improved. For example, since the first impurityregion 167 s has a shallow junction compared to the second impurityregion 167 d, and has a lower impurity density than that of the secondimpurity region 167 d, the leakage current, which may occur in thejunction of the first impurity region 167 s, may be reduced. Therefore,refresh characteristics of the memory device may be improved.

Furthermore, since the high density channel impurity region 168 isprovided below the second impurity region 167 d, and an impurity densityof the channel region below the first impurity region 167 s is lowerthan that of the high density channel impurity region 168, the leakagecurrent, which may occur in the junction of the first impurity region167 s, may be reduced. Therefore, electrical characteristics of thememory device can be improved.

Referring now to FIGS. 1, 11A, 11B, and 11C, semiconductor devicesaccording to some embodiments of the present invention will bediscussed. As illustrated therein, an isolation layer 109 is provided ina semiconductor substrate 100 having an active region A and a fieldregion F. The isolation layer 109 may be provided in the semiconductorsubstrate of the field region F, so as to define a plurality of activeregions A. An insulating liner 106 may be provided between the isolationlayer 109 and the semiconductor substrate 100. A buffer oxide layer 103may be provided between the insulating liner 106 and the semiconductorsubstrate 100. Upper gate electrodes UG, which cross the active region Aand extend to the isolation layer 109, may be provided. In someembodiments, the upper gate electrode UG located on the active region Amay be defined as an upper active gate electrode 257 a, and the uppergate electrode UG located on the isolation layer 109 may be defined asan upper field gate electrode 257 b.

A lower active gate electrode 255 a is provided, and the lower activegate electrode 255 a includes a first active gate electrode 254 a thatextends from the upper active gate electrode 257 a to the substrate ofthe active region A, and a second active gate electrode 251 a locatedbelow the first active gate electrode 254 a and having a greater widththan that of the first active gate electrode 254 a. In some embodimentsof the present invention, the second active gate electrode 251 a mayhave a circular shape as illustrated in FIG. 11A. Thus, electric fieldcrowding phenomenon between the second active gate electrode 251 a andthe active region A may be suppressed. Since the second active gateelectrode 251 a has a greater width than that of the first active gateelectrode 254 a, an effective channel length can be increased.

A lower field gate electrode 255 b may be provided, and the lower fieldgate electrode 255 b may include a first field gate electrode 245 b thatextends from the upper field gate electrode 257 b to the isolation layer109, and a second field gate electrode 251 b located below the firstfield gate electrode 254 b. The second field gate electrode may have agreater width than that of the first field gate electrode 254 b.

The second field gate electrode 251 b may have a bottom surface of alower level than that of the second active gate electrode 251 a. Here,the second field gate electrode 251 b may be provided on the sidewallsof the active region located below the second active gate electrode 251a. An upper surface of the second field gate electrode 251 b may belocated at a level higher than a bottom surface of the second activegate electrode 251 a.

As illustrated in FIGS. 11A and 11B, the first field gate electrode 254b has a bottom surface at a lower level than that of the first activegate electrode 254 a. It will be understood that embodiments of thepresent invention are not limited to the configuration. For example, insome embodiments of the present invention, the first field gateelectrode 254 b and the first active gate electrode 254 a may havebottom surfaces at a same level. Furthermore, the first field gateelectrode 254 b may have a bottom surface at a higher level than that ofthe first active gate electrode 254 a. The level positions of the bottomsurfaces of the first field gate electrode 254 b and the first activegate electrode 254 a may be designed appropriately in consideration ofrelations with impurity regions to be explained later.

The second field gate electrode 251 b may be provided to have a greaterwidth than that of the first active gate electrode 254 a. Furthermore,the second field gate electrode 251 b may be provided on the sidewallsof the active region located at both sides of the second active gateelectrode 251 a as well as to cover the sidewalls of the active regionlocated below the second active gate electrode 251 a. That is, thesecond field gate electrode 251 b may be provided to have a greaterwidth than that of the second active gate electrode 254. A gatedielectric layer 248 may be provided between the active region A and thegate electrode 261. The gate dielectric layer 248 may be, for example, asilicon oxide layer or a high-k dielectric layer.

First and second impurity regions 267 s and 267 d may be provided in theactive region located at both sides of the gate electrode 261. The firstimpurity region 267 s and the second impurity region 267 d may have anasymmetric structure. For example, the first impurity region 267 s maybe provided to have a shallow junction compared to the second impurityregion 267 d. Furthermore, the first impurity region 267 s may beprovided to have an impurity density lower than that of the secondimpurity region 267 d. In some embodiments of the present invention, thefirst and second impurity regions 267 s and 267 d may be defined assource and drain regions, respectively.

Furthermore, a high-density channel impurity region 268 may be providedbelow the second impurity region 267 d. The high-density channelimpurity region 268 has a conductivity type different from those of thefirst and second impurity regions 267 s and 267 d, and may have animpurity density higher than that of the channel region below the firstimpurity region 267 s.

As discussed above, since the lower active gate electrode 255 a isprovided in the active region A, transistors may be provided having anincreased effective channel length. Furthermore, since the lower fieldgate electrode 255 b is provided to cover the sidewalls of the activeregion located below the lower active gate electrode 255 a, transistorshaving an increased channel width may be provided. Therefore, a recessfin field effect transistor capable of increasing an effective channelwidth as well as an effective channel length may be provided accordingto some embodiments of the present invention.

Since the lower field gate electrode 255 b includes the first field gateelectrode 245 b, and the second field gate electrode 251 b has a greaterwidth than that of the first field gate electrode 254 b, the first andsecond impurity regions 267 s and 267 d may not overlap the lower fieldgate electrode 255 b. Since the sidewalls of the active region of thefirst and second impurity regions 267 s and 267 d may not overlap thelower field gate electrode 255 b, the electric field occurring betweenthe first and second impurity regions 267 s and 267 d, and the lowerfield gate electrode 255 b can be suppressed. As a result, the varianceof the threshold voltage of the transistor can be reduced according tosome embodiments of the present invention. Therefore, the electricalcharacteristics of transistors according to some embodiments of thepresent invention may be improved.

Although not illustrated in the Figures, a data storage element, whichis electrically connected to the first impurity region 267 s, may beprovided. The data storage element may be substantially similar to thedata storage element, which was discussed above with respect to FIG. 7.Since occurrence of an electric field between the first impurity region267 s and the lower field gate electrode 255 b may be suppressed, theleakage current generated in the first impurity region 267 s may bereduced. Therefore, the refresh characteristics of the memory device,such as a DRAM, may be improved.

Referring now to FIG. 12, semiconductor devices according to someembodiments of the present invention will be discussed. Transistorsaccording to embodiments of the present invention illustrated in FIG. 12are similar to transistors discussed above with reference to FIGS. 1,6A, 6B, and 6C. In particular, a gate electrode 361 having a recessedchannel in an active region of a semiconductor substrate 100 isprovided. In some embodiments of the present invention, the activeregion may be surrounded by an isolation layer. The gate electrode 361may include, for example, a lower active gate electrode 355 a providedin the active region, an upper gate electrode 357 protruding from anupper surface of the active region, and a metal layer 360 provided onthe upper gate electrode 357. The upper gate electrode 357 may extend tothe isolation layer. The lower active gate electrode 355 a may include afirst active gate electrode 354, and a second active gate electrode 351located below the first active gate electrode 354 and having a greaterwidth than that of the first active gate electrode 354.

A lower field gate electrode 355 b, which extends into the isolationlayer from the upper gate electrode 357 located on the isolation layer,may be provided. The lower field gate electrode 355 b may be provided onselected ones of the sidewalls of the active region located at bothsides of the lower active gate electrode 355 a as well as the sidewallsof the active region located below the lower active gate electrode 355a.

First and second impurity regions 367 s and 367 d may be provided in theactive region at both sides of the gate electrode 361. The first andsecond impurity regions 367 s and 367 d may have an asymmetric structurelike the asymmetric structure of the first and second impurity regions167 s and 167 d explained in reference to FIGS. 1, 6A, 6B, and 6C.Further, although not illustrated in the Figures, a high density channelimpurity region may be provided below the second impurity region 367 d.Furthermore, a data storage element, which is electrically connected tothe first impurity region 367 s, may be provided. The data storageelement may be substantially the same as the data storage elementdiscussed above with respect to FIG. 7.

When the data storage element including a capacitor dielectric layer iselectrically connected to the first impurity region 367 s, since thelower field gate electrode 355 b does not typically overlap the firstimpurity region 367 s, the leakage current, which may be generated inthe first impurity region 367 s, can be reduced and, thus, the refreshcharacteristics of the memory device, such as a DRAM, may be improved.Furthermore, since selected ones of the sidewalls of the active regionlocated at both sides of the lower active gate electrode 355 a iscovered, a fin effect can be improved.

Methods of fabricating semiconductor devices according to someembodiments of the present invention will now be discussed withreference to FIGS. 1 and 2A through 6C. Referring first to FIGS. 1, 2A,2B and 2C, a semiconductor substrate 100 is prepared. Regions of thesemiconductor substrate 100 may be divided into an active region A and afield region F. An isolation layer 109 for defining the active region Ais formed in the substrate of the field region F. The active region Ahas a major axis and a minor axis, and the active regions A may bealigned two-dimensionally in the major axis direction and the minor axisdirection.

The isolation layer 109 may be formed using a trench isolationtechnique. In particular, the formation of the isolation layer 109 mayinclude forming a trench in the substrate of the field region F, andforming an insulating layer filling the trench. After the trench isformed in the substrate of the field region F, a buffer oxide layer 103and an insulating liner 106 may be sequentially formed on the inner wallof the trench.

A sacrificial mask 130 having an opening 130 a crossing the activeregion A and extending to the isolation layer 109 may be formed on thesubstrate having the isolation layer 109. The sacrificial mask 130 maybe formed to include a pad insulating layer 121, a lower sacrificialmask 124, and an upper sacrificial mask 127, which are sequentiallystacked. Here, the pad insulating layer 121 may include, for example, asilicon oxide layer, and the lower sacrificial mask 124 may include, forexample, an insulating layer, such as a silicon nitride layer or asilicon oxynitride (SiON) layer. The upper sacrificial mask 127 mayinclude, an insulating layer, such as an amorphous carbon layer.

The opening 130 a of the sacrificial mask 130 may be formed to have apocket structure. In other words, the isolation layer exposed by theopening 130 a is a region in adjacent to the active region A, and theisolation layer disposed between the active regions A, which are alignedin the major axis, may be covered by the sacrificial mask 130.

Referring now to FIGS. 1, 3A, 3B, and 3C, the active region A exposed bythe opening 130 a, and the isolation layer 109 are etched using thesacrificial mask 130 as an etch mask, so as to form an upper activetrench 133 and a field trench 136. The bottom surface of the fieldtrench 136 may be formed to have a level lower than that of the upperactive trench 133. The upper active trench 133 and the field trench 136may be formed using an anisotropic etch process showing a high etch ratewith respect to the active region A and the isolation layer 109.

Furthermore, the upper active trench 133 and the field trench 136 may beformed by performing a first etch process using a first anisotropic etchprocess having a high etch rate with respect to either one of the activeregion A and the isolation layer 109, and by performing a second etchprocess using a second anisotropic etch process having a high etch ratewith respect to a remaining one.

After the isolation layer 109 exposed by the opening 130 a is etched, soas to form the field trench 136, the insulating liner and the bufferinsulating layer, which are exposed by the field trench 136, may beremoved.

Meanwhile, while the upper active trench 133 and the field trench 136are formed, the upper sacrificial mask 127 may be removed.

Referring to FIGS. 1, 4A, 4B and 4C, sidewall spacers 139 may be formedon the sidewalls of the upper active trench 133 and the field trench136. Here, the sidewall spacers 139 may be formed to cover the sidewallsof the exposed active region A. The sidewall spacers 139 may be formedof an insulating layer such as a silicon oxide layer, or a siliconnitride layer.

The active region A may be etched, using the sidewall spacers 139, thesacrificial mask 130, and the isolation layer 109 as etch masks. Here,the etching of the active region A using the sidewall spacers 139, thesacrificial mask 130, and the isolation layer 109 as etch masks mayinclude an isotropic etch process. As a result, a lower active trench142 having a greater width than that of the upper active trench 133 maybe formed below the upper active trench 133. Here, the lower activetrench 136 may be formed with a circular shape.

Referring, to now to FIGS. 1, 5A, 5B, and 5C, the sacrificial mask 130and the sidewall spacers 139 are removed. Thus, the upper active trench133 and the lower active trench 142 in the active region A may beexposed, and the sidewalls of the active region located below the loweractive trench 142 may be exposed. That is, the sidewalls of the activeregion located below the lower active trench 142 may be exposed by thefield trench 136. Here, the upper active trench 133 and the lower activetrench 142 may form an active trench 145. The active trench 145 and thefield trench 136 may form a gate trench.

Referring now to FIGS. 1, 6A, 6B, and 6C, a conductive layer and a hardmask 163 may be formed on the substrate having the active trench 145 andthe field trench 136, and the conductive layer may be etched using thehard mask 163 as an etch mask. As a result, a gate electrode 161covering the sidewalls of the active region located below the activetrench 145 may be formed while filling the active trench 145 and thefield trench 136. Here, the gate electrode 161 may be formed to have aprotrusion higher than an upper surface of the active region A.

The gate electrode 161 crossing the active region A may include, forexample, an upper active gate electrode 157 a crossing the active regionA, and a lower active gate electrode 155 a filling the active trench145. Here, the lower active gate electrode 155 a may include, forexample, a first active gate electrode 154, and a second active gateelectrode 151 located below the first active gate electrode 154 andhaving a greater width than that of the first active gate electrode 154.

The gate electrode 161 extending from the active region A to theisolation layer 109 may include, for example, an upper field gateelectrode 157 b located on the isolation layer 109, and a lower fieldgate electrode 155 a located in the isolation layer 109 and cover thesidewalls of the active region located below the lower active gateelectrode 155 a.

The gate electrode located between the active regions A aligned in themajor axis direction may include, for example, an upper field gateelectrode 157 b.

The gate electrode 161 may include, for example, a metal layer 160,which is formed on the upper active gate electrode 157 a and the upperfield gate electrode 157 b. The metal layer 160 may be, for example, atungsten layer, a nickel layer, a cobalt layer, a titanium layer, or ametal silicide layer.

Before the gate electrode 161 is formed, a gate insulating layer 148 maybe formed on the substrate having the active trench 145 and the fieldtrench 136. The gate insulating layer 148 may include, for example, asilicon oxide layer or a high-k dielectric layer. The gate insulatinglayer 148 may be formed using a semiconductor fabrication process, suchas thermal oxidation, chemical vapor deposition (CVD), or atomic layerdeposition (ALD).

Gate spacers 166 covering the sidewalls of the gate electrode 161 may beformed. The gate spacers 166 may include, for example, an insulatinglayer, such as a silicon nitride layer.

A first impurity region 167 s and a second impurity region 167 d may beformed on the active region at both sides of the gate electrode 161. Thefirst impurity region 167 s and the second impurity region 167 d may beformed to have an asymmetric structure. For example, the first impurityregion 167 s may be formed to have a shallow junction compared to thesecond impurity region 167 d. Furthermore, the first impurity region 167s may be formed to have a higher impurity density than that of thesecond impurity region 167 d. The first impurity region 167 s and thesecond impurity region 167 d may be formed to have a first conductivitytype.

A high density channel impurity region 168 may be formed in the channelregion below the second impurity region 167 d. Here, the high densitychannel impurity region 168 may be formed to have a higher impuritydensity than that of the channel region below the first impurity region167 s.

The first and second impurity regions 167 s and 167 d, and the highdensity channel impurity region 168 may be formed before the sacrificialmask 130 is formed. For example, after the first and second impurityregions 167 s and 167 d, and the high density channel impurity region168 are first formed by implanting impurity ions into predeterminedregions of the active region A, a process of forming the sacrificialmask 130 may be performed.

Thus, transistors, which comprise the first and second impurity regions167 s and 167 d, and the gate electrode 161, may be formed. That is,recess fin field effect transistors having a recessed channel structureand a fin structure may be formed.

As illustrated in FIG. 7, a data storage element 187, which iselectrically connected to the first impurity region 167 s, may be formedon the substrate having the transistors. In particular, a normalself-align contact process is performed on the substrate having thetransistors, thereby forming a first landing pad 169 s and a secondlanding pad 169 d, which respectively contact the first impurity region167 s and the second impurity region 167 d. A lower interlayerinsulating layer 172 may be formed on the substrate having the first andsecond landing pads 169 s and 169 d. A direct contact plug 175contacting the second landing pad 169 d through the lower interlayerinsulating layer 172 may be formed. A conductive line 178 covering thedirect contact plug 175 may be formed on the lower interlayer insulatinglayer 172. The conductive line 178 may be formed to have the directioncrossing the gate line 161. An upper interlayer insulating layer 181 maybe formed on the substrate having the conductive line 178. The upperinterlayer insulating layer 181 and the lower interlayer insulatinglayer 172 may form an interlayer insulating layer 182. A buried contactplug 184 contacting the first landing pad 169 s through the interlayerinsulating layer 182 may be formed.

A data storage element 187 covering the buried contact plug 184 may beformed on the interlayer insulating layer 182. The data storage element187 may comprise a capacitor dielectric layer. Thus, the semiconductordevice of the present invention may be used in a memory device such as aDRAM.

The data storage element 187 may include a nonvolatile data storagemedia. Here, the nonvolatile data storage media may include a resistancematerial layer, such as a phase change material layer.

Processing steps in the fabrication of semiconductor devices accordingto some embodiments of the present invention will now be discussed withrespect to FIGS. 1, and 8A through 11C. Referring first to FIGS. 1, 8A,8B, and 8C, a substrate 100 having an active region A and a field regionF is prepared. As discussed above with respect to FIGS. 2A, 2B, and 2C,a buffer oxide layer 103, an insulating liner 106, an isolation layer109, and a sacrificial mask 130 may be formed in the substrate 100.

The active region A and the isolation layer 109 are etched using thesacrificial mask 130 as an etch mask, thereby forming an upper activetrench 233 and an upper field trench 236. In this case, the upper activetrench 233 may be formed to have a bottom surface of a first depth Da1,and the upper field trench 236 may be formed to have a bottom surface ofa second depth Da2. The second depth Da2 is deeper than the first depthDa1. In particular, the upper active trench 233 and the upper fieldtrench 236 may be formed using, for example, an anisotropic etch processshowing a high etch rate with respect to the active region A and theisolation layer 109. In some embodiments of the present invention, theupper active trench 233 and the upper field trench 236 may be formed byperforming a first etch process using a first anisotropic etch processhaving a high etch rate with respect to either one of the active regionA and the isolation layer 109, and then, by performing a second etchprocess using a second anisotropic etch process having a high etch ratewith respect to a remaining one.

As illustrated in FIG. 8C, the buffer oxide layer 103, which is exposedby forming the upper active trench 233, may be removed. The buffer oxidelayer 103, which is exposed by forming the upper active trench 233, maybe removed while the upper active trench 233 and the upper field trench236 are formed.

Referring now to FIGS. 1, 9A, 9B, and 9C, sidewall spacers 239 may beformed to cover the sidewalls the upper active trench 233 and the upperfield trench 236. The sidewall spacers 239 may be formed of a materiallayer having an etch selectivity with respect to the active region A andthe isolation layer 239. For example, when the active region A is formedof a silicon substrate, and the isolation layer 239 is formed of asilicon oxide layer, the sidewall spacers 239 may be formed of a siliconnitride layer or a silicon oxynitride layer (SiON).

The active region A and the isolation layer 109 are etched using thesacrificial mask 130 and the sidewall spacers 239 as etch masks, therebyforming a lower active trench 242 having a greater width than that ofthe upper active trench 233, and a lower field trench 245 having agreater width than that of the upper field trench 236. The lower fieldtrench 245 may be formed to have a bottom surface at a lower level thanthat of the lower active trench 242. That is, the lower active trench242 may be formed to have a bottom surface at a third depth Db1, and thelower field trench 245 may be formed to have a bottom surface at afourth depth Db2. The fourth depth may be deeper than the third depthDb1. In particular, the lower active trench 242 and the lower fieldtrench 245 may be formed using an isotropic etch process showing a highetch rate with respect to the active region A and the isolation layer109. Alternatively, the lower active trench 242 and the lower fieldtrench 245 may be formed by performing a first etch process using afirst isotropic etch process having a high etch rate with respect toeither one of the active region A and the isolation layer 109, and then,by performing a second etch process using a second isotropic etchprocess having a high etch rate with respect to a remaining one.

Referring now to FIGS. 1, 10A, 10B, and 10C, the sacrificial mask 130and the sidewall spacers 239 may be removed. Furthermore, the insulatingliner 106 and the buffer oxide layer 103, which are exposed by the lowerfield trench 245, may be removed. As a result, the sidewalls of theactive region located below the lower active trench 242 may be exposed.Therefore, the active region located below the lower active trench 242may be formed to have a fin structure.

The upper active trench 233 and the lower active trench 242 may form anactive trench 243, and the upper field trench 236 and the lower fieldtrench 245 may form a field trench 246.

Referring now to FIGS. 1, 11A, 11B, and 11C, a conductive layer and ahard mask 263 may be formed on the substrate having the active trench243 and the field trench 246. The conductive layer may be etched usingthe hard mask 263 as an etch mask. As a result, a gate electrode 261 maybe formed to fill the active trench 243 and the field trench 246, and tocover the sidewalls of the active region located below the active trench243. Here, the gate electrode 261 may be formed to have a protrusionbeing higher than an upper surface of the active region A.

The gate electrode 261 crossing the active region A may comprise anupper active gate electrode 257 a crossing the active region A, and alower active gate electrode 255 a filling the active trench 243. Here,the lower active gate electrode 255 a may comprise a first active gateelectrode 254 a, and a second active gate electrode 251 a located belowthe first active gate electrode 254 a and having a greater width thanthat of the first active gate electrode 254 a.

The gate electrode 261 extending from the active region A to theisolation layer 109 may include, for example, an upper field gateelectrode 257 b on the isolation layer 109, and a lower field gateelectrode 255 b located in the isolation layer 109 and covering thesidewalls of the active region located below the lower active gateelectrode 255 a. In some embodiments of the present invention, the lowerfield gate electrode 255 b may include for example, a first field gateelectrode 254 b, and a second field gate electrode 251 b located belowthe first field gate electrode 254 b and having a greater width thanthat of the first field gate electrode 254 b. The second field gateelectrode 251 b may have a bottom surface having a lower level than thatof the second active gate electrode 251 a, and may cover the sidewallsof the active region located below the second active gate electrode 251a.

The gate electrode, which is located between the active regions Aaligned in the major axis direction, may include, for example, an upperfield gate electrode 257 b.

The gate electrode 261 may include, for example, a metal layer 260formed on the upper active gate electrode 257 a and the upper field gateelectrode 257 b. The metal layer 260 may be, for example, a cobaltlayer, a nickel layer, a tungsten layer, a titanium layer or a metalsilicide layer.

Before the gate electrode 261 is formed, a gate insulating layer 248 maybe formed on the substrate having the active trench 243 and the fieldtrench 246. The gate insulating layer 248 may be formed of a siliconoxide layer, or a high-k dielectric layer. The gate insulating layer 248may be formed using a semiconductor fabrication process, such as thermaloxidation, chemical vapor deposition (CVD), or atomic layer deposition(ALD).

Gate spacers 266 may be formed to cover the sidewalls of the gateelectrode 261. The gate spacer 266 may include an insulating layer, suchas a silicon nitride layer.

A first impurity region 267 s and a second impurity region 267 d may beformed in the active region at both sides of the gate electrode 261. Thefirst impurity region 267 s and the second impurity region 267 d may beformed to have an asymmetric structure. For example, the first impurityregion 267 s may be formed to have a shallow junction compared to thesecond impurity region 267 d. The first impurity region 267 s may beformed to have a lower impurity density than that of the second impurityregion 267 d. The first and second impurity regions 267 s and 267 d maybe formed to have a first conductivity type.

A high density channel impurity region 268 may be formed in the channelregion below the second impurity region 267 d. In some embodiments ofthe present invention, the high density channel impurity region 268 maybe formed to have a higher impurity density than that of the channelregion located below the first impurity region 267 s.

Meanwhile, the first and second impurity regions 267 s and 267 d, andthe high density channel impurity region 268 may be formed before thesacrificial mask 130 is formed. For example, after the first and secondimpurity regions 267 s and 267 d, and the high density channel impurityregion 268 may be formed first by implanting impurity ions intopredetermined regions of the active region A, a process of forming thesacrificial mask 230 may be performed.

Furthermore, a data storage element, which is electrically connected tothe first impurity region 267 s, may be formed using processing stepsdiscussed above with respect to FIG. 7.

Referring now to FIG. 12, processing steps in the fabrication ofsemiconductor devices according to some embodiments of the presentinvention will be discussed. As illustrated in FIG. 12, a gate electrode361 is formed to have a lower active gate 355 a located in an activeregion of a semiconductor substrate 100. Furthermore, the gate electrodeis formed to have a lower field gate electrode 355 b covering thesidewalls of the active region located at both sides of the lower activegate electrode 355 a as well as covering the sidewalls of the activeregion located below the lower active gate electrode 355 a. The gateelectrode 361 may further include an upper gate electrode 357, whichprotrudes from an upper surface of the active region. Here, the loweractive gate electrode 355 a may include, for example, a first activegate electrode 354, and a second active gate electrode 351, which islocated below the first active gate electrode 354 and has a greaterwidth than that of the first active gate electrode 354. Furthermore, thegate electrode 361 may include a metal layer 360 formed on the uppergate electrode 357.

Processing steps in the formation of the gate electrode 361 are similarto those discussed above with respect to the gate electrode 161 of FIGS.2A through 7. However, the mask used for etching the active region andthe mask used for etching the isolation layer are different. Inparticular, the sacrificial mask 130 as discussed above with respect toFIGS. 2A, 2B, and 2C may be used as a first mask etching the activeregion. As a result, the active trench 145 as discussed above withrespect to FIG. 5A may be formed. Furthermore, a second mask for etchingthe isolation layer is formed. Here, the second mask may be formed tohave an opening exposing a predetermined region of the isolation layer.The isolation layer is etched using the second mask as an etch mask,thereby forming a field trench exposing one of the sidewalls of theactive region located at both sides of the active trench 145 as well asexposing the sidewalls of the active region located below the activetrench 145 as illustrated in FIG. 5A. A gate electrode 361 may be formedto cover one of the sidewalls of the active region located at both sidesof the active trench as well as covering the sidewalls of the activeregion located below the active trench.

Before the gate electrode 361 is formed, a gate dielectric layer 348 maybe formed. A hard mask 363 may be formed on the gate electrode 361.Furthermore, gate spacers 366 may be formed to cover both sidewalls ofthe gate electrode 361.

First and second impurity regions 367 s and 367 d may be formed in theactive region at both sides of the gate electrode 361. The first andsecond impurity regions 367 s and 367 d may be formed to have anasymmetric structure. For example, the first impurity region 367 s maybe formed to have a shallow junction compared to the second impurityregion 367 d. The first impurity region 367 s may be formed to have alower impurity density than that of the second impurity region 367 d.Although not illustrated in the Figures, a high density channel impurityregion may be formed in the channel region below the second impurityregion 367 d. The high density channel impurity region 268 may be formedto have a higher impurity density than that of the channel regionlocated below the first impurity region 267 s.

As discussed above, some embodiments of the present invention provide atransistor that may be capable of reducing the occurrence of the bodyeffect while including a recessed channel. The transistor can suppress ashort channel effect. Furthermore, since the transistor has an increasedchannel width, the transistor can increase a driving current capability.In other words, the operating speed of the device may be improved.Furthermore, the transistor may reduce or possible suppressdeterioration of the transistor performance due to the body effect.

The gate electrode of the transistor may include a metal layer.Therefore, the semiconductor device using the transistor may improvesignal transmission speed.

Furthermore, since the transistor has an asymmetric structure of thesource region and the drain region, electrical properties of the memorydevice may be improved. In other words, since the impurity density ofthe source region is lower than that of the drain region, and theimpurity density of the channel region below the source region is lowerthan that of the channel region below the drain region, refreshcharacteristics of the memory device, such as DRAM, can be improved.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

1. A semiconductor device comprising: an isolation layer on asemiconductor substrate and defining an active region of thesemiconductor substrate; an upper gate electrode crossing over theactive region and extending to the isolation layer; a lower active gateelectrode including a first active gate electrode extending from theupper gate electrode to the active region and a second active gateelectrode below the first active gate electrode and having a greaterwidth than a width of the first active gate electrode; and a lower fieldgate electrode extending from the upper gate electrode to the isolationlayer and having a bottom surface that is at a lower level than a bottomsurface of the active gate electrode such that the sidewalls of theactive region are covered below the lower active gate electrode.
 2. Thesemiconductor device of claim 1, further comprising a first impurityregion and a second impurity region in an active region located on bothsides of the first upper gate electrode.
 3. The semiconductor device ofclaim 2, wherein the first impurity region and the second impurityregion have an asymmetric structure.
 4. The semiconductor device ofclaim 2, wherein the first impurity region has a shallow junctionstructure relative to a junction structure of the second impurityregion.
 5. The semiconductor device of claim 2, wherein the firstimpurity region has an impurity density lower than an impurity densityof the second impurity region.
 6. The semiconductor device of claim 2,further comprising a high density channel impurity region below thesecond impurity region, wherein the high density channel impurity regionhas a different conductivity type from conductivity types of the firstand second impurity regions, and wherein the high density channelimpurity region has an impurity density higher than an impurity densityof a channel region below the first impurity region.
 7. Thesemiconductor device of claim 2, further comprising a data storageelement electrically connected to the first impurity region.
 8. Thesemiconductor device of claim 1, wherein the upper gate electrode has agreater width than the widths of the first active gate electrode and thelower field gate electrode.
 9. A semiconductor device comprising: anisolation layer on a semiconductor substrate and defining an activeregion of the semiconductor substrate; an upper gate electrode crossingover the active region and extending to the isolation layer; a loweractive gate electrode including a first active gate electrode extendingfrom the upper gate electrode to the active region and a second activegate electrode below the first active gate electrode and having agreater width than a width of the first active gate electrode; and alower field gate electrode extending from the upper gate electrode tothe isolation layer and having a bottom surface that is at a lower levelthan a bottom surface of the active gate electrode such that thesidewalls of the active region are covered below the lower active gateelectrode. wherein the lower field gate electrode comprises a firstfield gate electrode and a second field gate electrode below the firstfield gate electrode, wherein the second field gate electrode has agreater width than a width of the first field gate electrode.
 10. Thesemiconductor device of claim 9, wherein the second field gate electrodehas a greater width than a width of the first active gate electrode. 11.The semiconductor device of claim 9, wherein the second field gateelectrode is formed to cover the sidewalls of the active region locatedat both sides of the second active gate electrode as well as to coverthe sidewalls of the active region located below the second active gateelectrode.
 12. The semiconductor device of claim 11, wherein the secondfield gate electrode has a greater width than a width of the secondactive gate electrode.
 13. The semiconductor device of claim 9, whereinan upper surface of the second field gate electrode is higher than abottom surface of the second active gate electrode.
 14. Thesemiconductor device of claim 9, further comprising a first impurityregion and a second impurity region in an active region located on bothsides of the first upper gate electrode.
 15. The semiconductor device ofclaim 14, wherein sidewalls of the active region of the first and secondimpurity regions do not overlap the lower field gate electrode.
 16. Thesemiconductor device of claim 14, wherein the first impurity region andthe second impurity region have an asymmetric structure.
 17. Asemiconductor device comprising: an isolation layer on a semiconductorsubstrate and defining an active region of the semiconductor substrate;an upper gate electrode crossing over the active region and extending tothe isolation layer; a lower active gate electrode including a firstactive gate electrode extending from the upper gate electrode to theactive region and a second active gate electrode below the first activegate electrode and having a greater width than a width of the firstactive gate electrode; and a lower field gate electrode extending fromthe upper gate electrode to the isolation layer and having a bottomsurface that is at a lower level than a bottom surface of the activegate electrode, wherein the lower field gate electrode is disposed tooverlap one of the sidewalls of the active region located on both sidesof the lower active gate electrode and does not overlap the other ofsidewalls of the active region located on both sides of the lower activegate electrode.
 18. The semiconductor device of claim 17, furthercomprising a first impurity region and a second impurity region in anactive region located on both sides of the first upper gate electrode.19. The semiconductor device of claim 18, wherein the first impurityregion does not overlap the lower field gate electrode.
 20. Thesemiconductor device of claim 18, further comprising a data storageelement electrically connected to the first impurity region.